Criticisms Mount Over HBM Efficiency Amidst Speculation of High Bandwidth Flash
The semiconductor industry is facing growing scrutiny regarding the long-term viability of High Bandwidth Memory (HBM) as the primary solution to the “memory wall” problem. During a Q&A session at the Hot Chips 2026 conference, industry analysts and executives raised concerns regarding the diminishing returns of increasing HBM stack heights.
According to reports circulating on Reddit, a former Intel CEO characterized HBM as “lousy,” suggesting that the current trajectory of memory architecture may be inefficient. These criticisms center on the physical limitations of stacking memory layers to achieve higher capacity and bandwidth.
The Diminishing Returns of Vertical Stacking
The technical debate focuses on the trade-offs involved in increasing the number of layers in a memory stack. During the Hot Chips 2026 event, Irrational Analysis questioned the industry’s focus on increasing stack height rather than increasing raw speed.
The critique posits that as stacks reach higher levels—potentially up to 20 layers in HBM4—the throughput per layer may be significantly diluted. Specifically, the analysis suggests that a 20-layer stack might only provide 20% of the bandwidth of a single chip per layer, potentially causing each core die to operate slower than standard commodity memory.
This sentiment was echoed by a Vice President at SK HYNIX INC, who stated that HBM is “not the final answer to the memory wall problem.” The discussion suggests that the industry may eventually pivot toward “High Bandwidth Flash” to address these throughput and efficiency limitations.
Market Speculation and Technical Counterpoints
While the criticisms of HBM are gaining traction in technical forums, some observers remain skeptical of the transition to new architectures. Unverified commentary on Reddit suggests that Intel Corp could face significant financial risks if it invests heavily in HBM-based flash technology only to find a lack of market demand.
Conversely, some technical contributors argue that current HBM layer stacks are not actually as tall as critics suggest, implying that the “dilution” of throughput may be overstated. Other discussions have explored alternative software-level solutions, such as caching updated weights in RAM to minimize the frequency of full model rewrites during back-propagation.
As the industry moves toward more mature AI models, speculation remains regarding whether future architectures will move away from external storage mediums entirely, potentially encoding weights directly into silicon to maximize performance.